Logic Unit

  • Performs logical operations on the two inputs A and B and produces the output out the top. The operation select comes in from the right and is copied out to the left so that they can be chained together.
  • For example, data inputs of
    1010
    on A and
    0010
    on B, with a control signal of
    0001
    would give the result
    0010
    on the output.
  • NOT works with Input A only.
XX00
NOT
XX01
AND
X110
OR
X111
XOR

Arithmetic Unit (AU)

  • Performs arithmetic and comparison operations simultaneously on the two inputs A and B.
  • The control input chooses a combination of both an arithemetic operation and a boolean operation, with each result going to a seperate data output (arithmetic: right, comparison: left).
  • The control signal (bit 0 and bit 1) are passed through, and bit 2 indicates whether there is an overflow on the arithmetic result, causing a carry. This means two AU's can be chained to work on numbers larger than 4 bits.
  • Subtraction is carried out by performing (A + ¬B) + 1, since -B = ¬B + 1 in the two’s complement system. For some reason they were implemented such that the +1 comes from the bit 2 on the control input. So for subtraction your control signal must be
    X111
    or
    X110
XX00
 A + B  / ARTH == 0?

XX01
 Pass A / ARTH == 0?

XX10
 A - B  / A == B?

XX11
 A - B  / A < B?

Non-Volatile Memory

  • Stores up to 32,768 bytes of memory (addressed by 15 not 16 bits as the top bit is not connected), with the memory width also being a byte (8 bits).
  • The non-volatile memory persists through loss of power.
  • Memory is accessed through 4 address inputs (in green).
  • Address ports default to 0, so smaller regions of memory can be accessed while using a subset of the address ports. (leave the other unconnected)
  • Control input is passed to control output.
XXX1
Clock bit
X1XX
Enable bit
X1X1
input is written IF enable bit == 1 and the clock bit == 1 and the write jumper cable is in place

Register (REG)

  • Registers store their inputs when enabled and the clock is high and constantly output whatever is stored in them.
  • The default state of the control is
    X101
    . This means that if left unconnected the register becomes transparent
  • The reset signal generally comes from the clock.
XXX1
Clock bit
X1XX
Enable bit
X1X1
input is written IF enable bit == 1 and the clock bit == 1
XX1X
Reset to 0000 regardless of the other bits set

Clock

  • Outputs alternating clock signals on its two outputs.
  • Can be used in either manual or auto mode, with the 'A/M' switch indicated on the diagram.
  • The frequency of the clock can be adjusted through the rotary switch, indicated by 'SPD' in the diagram.
  • The frequency can be further adjusted by flicking the switch, indicated by 'RAT' in the diagram, that will make the clock 1000x faster.
  • In manual mode, the clock is advanced by pressing the button indicated by 'MAN' in the diagram.
  • The clock can be reset to Time 0 by pressing the button indicated by 'RES'. This also sends out
    0010
    on both outputs which will reset any registers connected to the clock.
  • Has a power jack that if connected to a plug will distribute power over the data cables to all other modules.
Time 0: A
0000
B
0000

Time 1: A
0001
B
0000

Time 2: A
0000
B
0000

Time 3: A
0000
B
0001

Input

  • Each bit of the data output if controlled by one of the 4 switches. (careful! the switches are labeled 1-4 not 0-3 like they should)
  • Also can distribute power from its power jack.

Demultiplexor

  • The demultiplexer takes 1 input and, based on the 2 least significatn bits of the control input, selects 1 of the 4 outputs to pass the signal to.
  • The control input is passed to the control output.
  • Careful! with an input of 0 it will select the left most output which makes snece to english speakers but not really mathmatically or in computer science.
XX00
Select output A
XX01
Select output B
XX10
Select output C
XX11
Select output D

Multiplexor

  • The multiplexer takes 4 inputs and selects one of them based on the 2 east significatn bits of the control input. (same ordering problem as demultiplexer)
  • The control input is passed to the control output.
XX00
Select input A
XX01
Select input B
XX10
Select input C
XX11
Select input D

4 Way Fanout

  • Takes an input and repeats it to all 4 outputs.

Split / Merge

  • This is a tricky component. There is no logic in it... just electrical connections. So for instance if you connect both of the split inputs (E and F) you will get undefined behavoir.
  • It has been designed only to work in a couple of use cases so does not work as you would expect all the time.
    - To extract the lowest two bits or the higher two bits (for use when creating a 1 to 16 demultiplexer)
    - To extract just bit 1 or bit 3
    - To merge the two lowest bits from the clock signal with an enable signal from some contol logic (to be placed in bit 2) to create a 4bit control signal for a component.
  • The connections are as follows

Right Shift

  • Shifts the data input, indicated by 'D' in the diagram, to the right.
  • Can either pass the data signal through (shift 0) or shift 1, 2 or 3 places to right, depending on control signal
  • For example, given a data input of
    0010
    and a control input of
    0010
    , the output would be
    1000
    .
  • The carry signal, indicated by 'C' in the diagram, carrys the overflow of the bits in to a connected right shifter. This means words longer than 4 bits can be shifted.
  • Careful! The carry signal may be confusing when inspected (for instance when shifting 0 places it gives an undefined output), but works correctly when connected to a right shifter since this value is never used.
XX00
Pass signal
XX01
Shift by 1
XX10
Shift by 2
XX11
Shift by 3

Left Shift

  • Shifts the data input, indicated by 'D' in the diagram, to the left.
  • Can either pass the data signal through or shift 1, 2 or 3 places to left.
  • For example, given a data input of
    0001
    and a control input of
    0001
    , the output would be
    0010
    .
  • The carry signal, indicated by 'C' in the diagram, carrys the overflow of the bits in to a connected left shifter. This means words longer than 4 bits can be shifted.
  • Careful: The carry signal again may be confusing since when shift is 0 gives undefined output, but works correctly when connected to a left shifter.
XX00
Pass signal
XX01
Shift by 1
XX10
Shift by 2
XX11
Shift by 3

Chained OR

  • Performs an OR on the least significant bit of the 4 inputs and the control input, i.e. If any of them are of the form
    XXX1
    , then the output will be
    0001
    , else it will be
    0000
    .
  • Each of the 4 inputs is also passed through to its opposite pairing.